1. Field of the Invention
The present invention relates to a liquid crystal display (LCD), and more particularly to a chip-on-glass type liquid crystal display in which each wiring for driver circuits is directly formed on an LCD panel.
2. Description of the Prior Art
An active matrix type LCD includes a plurality of thin film transistors (hereinafter, referred to as “TFTs”), which are located around intersectional points between a plurality of scan lines and a plurality of signal lines, and by which a plurality of liquid crystal pixels are driven. The scan lines are each connected to an external gate driver IC, which provides scan signals. The signal lines are each connected to an external source driver IC, which provides image signals. When the image signals inputted from the source driver IC are applied to liquid crystals through the TFTs turned on by the scan signals, a designated image is displayed.
There are various methods of connecting the scan lines to the gate driver IC and of connecting the signal lines to the source driver IC, for example, TAB (Tape Automated Bonding) using a printed circuit board, and chip-on-glass (hereinafter, referred to as “COG”). In the COG method, both a gate driver IC and a source driver IC are directly attached onto an LCD panel by soldering or a metallic paste, and similarly each wiring for the gate driver IC and the source driver IC is directly performed on the LCD panel. In general, the wiring formed directly on the panel by application of this COG technology is referred to as “panel wiring”. Herein, the gate driver IC and the source driver IC are together generically referred to as a “driver circuit”. Further, a voltage applied to each driver circuit in order to drive the driver circuit is called a “driving voltage”.
FIG. 1 shows how a driving voltage is applied to respective driver circuits 102, 104 and 106 through each panel wiring between the driver circuits. Each panel wiring can be modeled into resistors Rn−1 and Rn. As shown in FIG. 1, when the panel wirings Rn−1 and Rn for supplying the driving voltage to the driver circuits 102, 104 and 106 are connected in series between the driver circuits 102, 104 and 106, a voltage drop is generated by internal resistance components of the driver circuits 102, 104 and 106 and by resistance components of the panel wirings Rn−1 and Rn. Owing to this voltage drop, a relationship as the following Formula 1 is established:Vo(n−1)>Vi(n)>Vo(n)>Vi(n+1)  Formula 1
where Vi(n) is the input driving voltage applied to the driver circuit 104 in reality, and Vo(n) is the output driving voltage outputted from the driver circuit 104 in order to drive next circuit.
For this reason, when several driver circuits are connected with each other, an input driving voltage applied actually to a driver circuit after a certain step drops less than the minimum voltage (referred to as an “operation voltage”) necessary to operate the driver circuit, so that the circuit may not perform normal operation.